Here is the description of Register Organization:
Register
A register is a small, high-speed storage location within the CPU (Central Processing Unit) of a computer that is used to store temporary data and instructions that are actively being processed by the CPU.
• They are fast but have limited capacity compared to main memory (RAM).
Register Organization
Register organization refers to the way registers are structured and managed within the CPU. This includes the arrangement of different types of registers, such as data registers, address registers, and control registers.
• Efficient register organization is crucial for optimizing the performance of the CPU and ensuring smooth execution of instructions.
General register organization refers to the arrangement and management of various types of registers within the Central Processing Unit (CPU) of a computer system. These registers play essential roles in the execution of instructions and the manipulation of data within the CPU.
- These registers are used for various computational and data manipulation tasks during program execution.
- The organization typically defines the number of registers available, their size, and their specific roles, including temporary data storage, addressing, and operand manipulation.
- The organization of general registers can vary between different CPU architectures and designs, impacting the CPU’s performance and capabilities.
Block Diagram of General Register Organization:
The below image depicts the general organization of seven CPU registers:
The control unit is in charge of the CPU bus system. The control unit specifies the data flow via the ALU by selecting the ALU’s function and system components.
Let us consider R1←R2 + R3, and the functions implemented within the CPU are as follows:
| Function name | Description |
| MUX A Selector (SELA) | It can insert R2 into bus A. |
| MUX B Selector (SELB) | It can insert R3 in bus B. |
| ALU Operation Selector (OPR) | It can select the arithmetic addition(ADD). |
| Decoder Destination Selector (SELD) | It can transfer the result into R1. |
The buses are used to perform the multiplexers of 3-state gates. The control word is determined by the status of 14 binary selection inputs. The 14-bit control word defines the micro-operation.
Control Word:
A control word typically refers to a binary word or a group of bits used to control various operations or configurations within a system.
There are 14 binary selection inputs in the unit, and the combined value specifies a control word.
Encoding of Register Selection Field:
The table specifies the encoding of register selection fields:
| Binary Code | SELA | SELB | SELD |
| 000 | Input | Input | None |
| 001 | R1 | R1 | R1 |
| 010 | R2 | R2 | R2 |
| 011 | R3 | R3 | R3 |
| 100 | R4 | R4 | R4 |
| 101 | R5 | R5 | R5 |
| 110 | R6 | R6 | R6 |
| 111 | R7 | R7 | R7 |
Encoding of ALU Operations:
The table shows a few of the operations that the ALU performs.
| OPR Select | Operation | Symbol |
| 00000 | Transfer A | TSFA |
| 00001 | Increment A | INCA |
| 00010 | Add A + B | ADD |
| 00101 | Subtract A – B | SUB |
| 00110 | Decrement A | DECA |
| 01000 | ADD A and B | AND |
| 01010 | OR A and B | OR |
| 01100 | XOR A and B | XOR |
| 01110 | Complement A | COMA |
| 10000 | Shift right A | SHRA |
| 11000 | Shift left A | SHLA |
Examples of Microoperations:
Here is the Examples of Microoperations for the CPU:
| Micro-operation | SELA | SELB | SELD | OPR | Control Word |
| R1 ← R2 – R3 | R2 | R3 | R1 | SUB | 010 011 001 00101 |
| R4 ← R4 ∨ R5 | R4 | R5 | R4 | OR | 100 101 100 01010 |
| R6 ← R6 + R1 | – | R6 | R1 | INCA | 110 000 110 00001 |
| R7 ← R1 | R1 | – | R7 | TSFA | 001 000 111 00000 |
| Output ← R2 | R2 | – | None | TSFA | 010 000 000 00000 |
| Output ← Input | Input | – | None | TSFA | 000 000 000 00000 |
| R4 ← shl R4 | R4 | – | R4 | SHLA | 100 000 100 11000 |
| R5 ← 0 | R5 | R5 | R5 | XOR | 101 101 101 01100 |
Note:
Field:
SELA, SELB, SELD, OPR
Symbol:
R2, R3, R1, SUB
Control Word:
010, 011, 001, 00101
