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Instruction Pipelining

Here is the description of Instruction Pipelining:

An instruction pipelining is a fundamental concept in computer architecture, representing a technique used to improve the throughput and efficiency of instruction execution in a processor.

  • It involves breaking down the execution of an instruction into multiple stages, allowing multiple instructions to be in various stages of execution simultaneously.
  • This overlapping of stages enables the processor to achieve higher performance by reducing the overall time taken to execute a sequence of instructions.

In the most general case computer needs to process each instruction in following sequence of steps:

  • Fetch the instruction from memory (FI).
  • Decode the instruction (DA).
  • Calculate the effective address.
  • Fetch the operands from memory (FO).
  • Execute the instruction (EX).
  • Store the result in the proper place.
  • Assume that the decoding of the instruction can be combined with the calculation of the effective address into one segment.
  • Assume further that most of the instructions place the result into a processor register so that the instruction execution and storing of the result can be combined into one segment. This reduces the instruction pipeline into four segments.
  • Below Figure shows how the instruction cycle in the CPU can be processed with a four-segment pipeline. While an instruction is being executed in segment 4, the next instruction in sequence is busy fetching an operand from memory in segment 3.
  • The effective address may be calculated in a separate arithmetic circuit for the third instruction, and whenever the memory is available, the fourth and all subsequent instructions can be fetched and placed in an instruction FIFO.
  • Thus up to four suboperations in the instruction cycle can overlap and up to four different instructions can be in progress of being processed at the same time.
  • Once in a while, an instruction in the sequence may be a program control type that causes a branch out of normal sequence.
  • In that case the pending operations in the last two segments are completed and all information stored in the instruction buffer is deleted. The pipeline then restarts from the new address stored in the program counter.
  • Similarly, an interrupt request, when acknowledged, will cause the pipeline to empty and start again from a new address value.
  • Below Figure shows the operation of the instruction pipetine. The time in the horizontal axis is divided into steps of equal duration. The four segments are represented in the diagram with an abbreviated symbol.
  • 1. F1 is the segment that fetches an instruction. 2. DA is the segment that decodes the instruction and calculates the effective address. 3. FO is the segment that fetches the operand. 4. EX is the segment that executes the instruction.
  • It is assumed that the processor has separate instruction and data memories so that the operation in Fl and FO can proceed at the same time. In the absence of a branch instruction, each segment operates on different instructions.
Screenshot 2024 04 06 203246
  • Thus, in step 4, instruction 1 is being executed in segment EX; the operand for instruction 2 is being fetched in segment FO; instruction 3 is being decoded in segment DA; and instruction 4 is being fetched from memory in segment FL Assume now that instruction 3 is a branch instruction.
  • As soon as this instruction is decoded in segment DA in step 4, the transfer from FI to DA of the other instructions is halted until the branch instruction is executed in step 6. If the branch is taken, a new instruction is fetched in step 7.
  • If the branch is not taken, the instruction fetched previously in step 4 can be used. The pipeline then continues until a new branch instruction is encountered. Another delay may occur in the pipeline if the EX segment needs to store the result of the operation in the data memory while the FO segment needs to fetch an operand. In that case, segment FO must wait until segment EX has finished its operation.
  • In general, there are three major difficulties that cause the instruction pipeline to deviate from its normal operation.
  • 1. Resource conflicts caused by access to memory by two segments at the same time. Most of these conflicts can be resolved by using separate instruction and data memories.
  • 2. Data dependency conflicts arise when an instruction depends on the result of a previous instruction, but this result is not yet available.
  • 3. Branch difficulties arise from branch and other instructions that change the value of PC.

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