Microprocessor and Computer Architecture Model Question and Solutions

Model Question

Microprocessor and CO(IT 239)

Group ” A”

Brief Answer Questions:

1. Define the terms microprocessor and computer Architecture.

Ans: Microprocessor is a digital device on a chip that can fetch instructions from memory, decode and execute them and give results. A Microprocessor is an important part of a computer architecture without which you will not be able to perform anything on your computer.

Computer Architecture can be defined as a set of rules and methods that describe the functionality, management and implementation of computers. To be precise, it is nothing but rules by which a system performs and operates .

2. If A=101101 , what is the value of A after performing circular shift Right?

Ans: In circular shift right operation each bit in the register is shifted to the right one by one. After shifting, the MSB becomes empty, so the value of the LSB is filled in there.

So, the value of A will be 110110 after circular right shift.

3. Define term operand.

Ans: An operand is the second part of the instruction, which tells the computer where to find or store the data or instructions. The number of operands varies among computers.

5. List the registers of Intel 8085 microprocessor.

Ans: Registers of Intel 8085 microprocessor are:

a. General Purpose Registers

b. Specific Purpose Registers

c. Memory Registers

6. Define Associative memory.

Ans: An associative memory can be considered as a memory unit whose stored data can be identified for access by the content of the data itself rather than by an address or memory location .Associative memory is also known as Content Addressable Memory (CAM).

7. Explain left logical shift.

Ans: In logical left shift, one position moves each bit to the left one by one. The Empty least significant bit (LSB) is filled with zero, and the most significant bit (MSB) is rejected.

Example:

8. Draw the Block Diagram of microprocessor.

A microprocessor consists of an ALU, control unit and register array. Where ALU performs arithmetic and logical operations on the data received from an input device or memory. Control unit controls the instructions and flow of data within the computer. And, register array consists of registers identified by letters like B, C, D, E, H, L, and accumulator.

9. What is memory space and address space?

Ans: Addresses that are used by programmers are known as virtual addresses, and the set of such addresses is known as the address space. The address space is the set of addresses generated by programs as they reference instructions and data.

Space where the address is saved in the main memory is referred to as location or physical address and the set of such locations is known as the memory space .The memory space holds the actual main memory locations that are directly addressable for processing.

10. Define general register CPU organization.

Ans: When we are using multiple general-purpose registers, instead of a single accumulator register, in the CPU Organization then this type of organization is known as General register-based CPU Organization. In this type of organization, the computer uses two or three address fields in their instruction format.

Group “B”

Short Answer Questions(Attempt any 5 questions):

11. Explain about Hardware implementation of logic micro operation with its functional table.

Ans: Here is the explanation of Hardware implementation of logic micro operation with its functional table:

• The hardware implementation of logic microoperations requires that logic gates be inserted for each bit or
  pair of bits in the registers to perform the required logic function.
• Although there are 16 logic microoperations, most computers use only four- AND, OR, XOR
  (exclusive-OR), and complement from which all others can be derived.
• Block diagram shows one stage of a circuit that generates the four basic logic microoperations.
• It consists of four gates and a multiplexer. Each of the four logic operations is generated through a
  gate that performs the required logic.
• The outputs of the gates are applied to the data inputs of the multiplexer. The two selection inputs S1 and S0
  choose one of the data inputs of the multiplexer and direct its value to the output.

Function Table:

12. Why we need IOP? Explain

Ans: The Input-Output Processor (IOP) is just like a CPU that handles the details of I/O operations. It is more equipped with facilities than those available in a typical DMA controller. The IOP can fetch and execute its own instructions that are specifically designed to characterize I/O transfers. In addition to the I/O-related tasks, it can perform other processing tasks like arithmetic, logic, branching, and code translation. The main memory unit takes a pivotal role. It communicates with the processor by means of DMA.

The Input-Output Processor is a specialized processor which loads and stores data in memory along with the execution of I/O instructions. It acts as an interface between the system and devices. It involves a sequence of events to execute I/O operations and then store the results in memory. 

We need IOP for the following purposes:

• I/O processors can be used in data acquisition systems to acquire and process data from various sensors and input devices. The I/O processor can handle high-speed data transfer and perform real-time processing of the acquired data.
• I/O processors can be used in storage systems to handle the input and output of data to and from storage devices. The I/O processor can handle high-speed data transfer and perform data caching and prefetching operations.
• I/O processors can be used in industrial control systems to interface with various control devices and sensors. The I/O processor can provide precise timing and control signals, and can also perform local processing of the input data.

13. Explain about Hardwired control unit of basic computers.

Ans: A hardwired control unit is a control unit that uses a fixed set of logic gates and circuits to execute instructions. The control signals for each instruction are hardwired into the control unit, so the control unit has a dedicated circuit for each possible instruction. Hardwired control units are simple and fast, but they can be inflexible and difficult to modify.

Characteristics of Hardwired Control Unit:

• The decoder’s outputs are denoted by the letters D0 through D7.
• The bit 15 operation code is transferred to a flip-flop with the symbol I.
• The control logic gates are programmed with operation codes from bits 0 to 11.
• The sequence counter (or SC) can count from 0 to 15 in binary.

14. List Arithmetic instruction of Intel 8085 microprocessor.

Ans: Arithmetic Instructions are the instructions which perform basic arithmetic operations such as addition, subtraction and a few more.

Following is the table showing the list of arithmetic instructions:

15. Define cache mapping. List the types of cache mapping techniques,

Ans: Cache mapping refers to a technique using which the content present in the main memory is brought into the memory of the cache. The process of cache mapping helps us define how a certain block that is present in the main memory gets mapped to the memory of a cache in the case of any cache miss.

There are three types of cache mapping technique :

• Direct Mapping
• Associative Mapping
• Set-Associative Mapping

‣Direct Mapping

In direct mapping physical address is divided into three parts i.e., Tag bits, Cache Line Number and Byte offset. The bits in the cache line number represents the cache line in which the content is present whereas the bits in tag are the identification bits that represents which block of main memory is present in cache. The bits in the byte offset decides in which byte of the identified block the required content is present.

‣Fully Associative Mapping

In fully associative mapping address is divided into two parts i.e., Tag bits and Byte offset. The tag bits identify that which memory block is present and bits in the byte offset field decides in which byte of the block the required content is present.

‣Set Associative Mapping

In set associative mapping the cache blocks are divided in sets. It divides address into three parts i.e., Tag bits, set number and byte offset. The bits in set number decides that in which set of the cache the required block is present and tag bits identify which block of the main memory is present. The bits in the byte offset field gives us the byte of the block in which the content is present.

16.A non pipeline system takes 150 ns to process a task. The same task can be processed in eight-segment pipeline with clock cycle time of 14ns. Determine the speed up ratio of pipeline for 1000 tasks.

Ans: To determine the speedup ratio of the pipeline system compared to the non-pipeline system for processing 1000 tasks, we first need to calculate the total time taken by each system to process 1000 tasks.

For the non-pipeline system: Total time = Number of tasks × Time per task Total time = 1000 tasks × 150 ns/task Total time = 150,000 ns

For the pipeline system: Since the pipeline system has a clock cycle time of 14 ns, we need to calculate the total number of clock cycles required to process 1000 tasks.

Total number of clock cycles = Number of tasks × Number of pipeline stages

Each task passes through 8 pipeline stages, so: Total number of clock cycles = 1000 tasks × 8 stages = 8000

Total time for the pipeline system = Total number of clock cycles × Clock cycle time Total time for the pipeline system = 8000 cycles × 14 ns/cycle Total time for the pipeline system = 112,000 ns

Now, we can calculate the speedup ratio:

Speedup ratio = Time taken by non-pipeline system / Time taken by pipeline system Speedup ratio = 150,000 ns / 112,000 ns Speedup ratio ≈ 1.3393

So, the speedup ratio of the pipeline system compared to the non-pipeline system for processing 1000 tasks is approximately 1.3393.

Group “C”

Long Answer Questions(Attempt any 3):

17. Why we need addressing modes? explain any 5 types of addressing modes in details.

Ans: The term addressing modes refers to the way in which the operand of an instruction is specified. The addressing mode specifies a rule for interpreting or modifying the address field of the instruction before the operand is actually executed.

We need addressing modes as it help us specify the way in which an operand’s effective address is represented in any given instruction. Some addressing modes allow referring to a large range of areas efficiently, like some linear array of addresses along with a list of addresses.

Few of the addressing modes are listed below

1. Immediate Addressing Mode – 
   In immediate addressing mode the source operand is always data. If the data is 8-bit, then the instruction will be of 2 bytes, if the data is of 16-bit then the instruction will be of 3 bytes.  Examples: 
   MVI B 45 (move the data 45H immediately to register B) 
   LXI H 3050 (load the H-L pair with the operand 3050H immediately) 
   JMP address (jump to the operand address immediately)

   2. Register Addressing Mode – 
In register addressing mode, the data to be operated is available inside the register(s) and register(s) is(are) operands. Therefore the operation is performed within various registers of the microprocessor.  Examples: 
MOV A, B (move the contents of register B to register A) 
ADD B (add contents of registers A and B and store the result in register A) 
INR A (increment the contents of register A by one) 

3. Direct Addressing Mode – 
In direct addressing mode, the data to be operated is available inside a memory location and that memory location is directly specified as an operand. The operand is directly available in the instruction itself.  Examples: 
LDA 2050 (load the contents of memory location into accumulator A) 
LHLD address (load contents of 16-bit memory location into H-L register pair) 
IN 35 (read the data from port whose address is 35) 

4.Register Indirect Addressing Mode – 
In register indirect addressing mode, the data to be operated is available inside a memory location and that memory location is indirectly specified by a register pair.  Examples: 
MOV A, M (move the contents of the memory location pointed by the H-L pair to the accumulator) 
LDAX B (move contents of B-C register to the accumulator) 
STAX B (store accumulator contents in memory pointed by register pair B-C)   

5.Implied/Implicit Addressing Mode – 
In implied/implicit addressing mode the operand is hidden and the data to be operated is available in the instruction itself.  Examples: 
CMA (finds and stores the 1’s complement of the contents of accumulator A in A) 
RRC (rotate accumulator A right by one bit) 
RLC (rotate accumulator A left by one bit)

18.Why we need priority interrupt? Explain serial priority interrupt method with suitable block diagram.

Ans: A priority interrupt is a system which decides the priority at which various devices, which generates the interrupt signal at the same time, will be serviced by the CPU. The system has authority to decide which conditions are allowed to interrupt the CPU, while some other interrupt is being serviced.

A priority interrupt is needed as it is a system that determines the priority at which devices generating interrupt signals simultaneously should be serviced by the CPU first. High-speed transfer devices are generally given high priority, and slow devices have low priority.

The aerial priority interrupt method involves connecting all the devices that can request an interrupt in a serial manner. This configuration is governed by the priority of the devices. The device with the highest priority is placed first followed by the second highest priority device and so on. The given figure depicts this arrangement.

This method uses hardware to establish the priority of simultaneous interrupts. Deciding the interrupt priority includes the serial connection of all the devices that generate an interrupt signal. The devices are placed according to their priority such that the device having the highest priority gets placed first, followed by lower priority devices. The device with the lowest priority is found at last within the chain. In the daisy-chaining device, all devices are linked in serial form. The interrupt line request is not unusual to devices.

19. Perform (-19)*(+13) by booth multiplication algorithm.

Ans: To perform (-19) * (+13) using Booth’s Multiplication Algorithm, we first represent the numbers in binary:

-19: 10101 (because -19 = -16 + (-2) + (-1) = -16 + 2^4 + 2^1 + 2^0 = 10101 in binary) +13: 01101

Now, let’s follow the steps of Booth’s Multiplication Algorithm:

1. Initialize two registers, A and Q, with the binary representations of the numbers to be multiplied. Here, A will be the multiplicand (-19) and Q will be the multiplier (+13).A = 10101 Q = 01101
2. Initialize another register, Q0, with 0. This register will store the previous value of Q0 for booth’s algorithm.Q0 = 0
3. Repeat the following steps for the number of bits in the multiplier (5 bits in this case):a. If the last two bits of Q and Q0 are “01” or “10”, perform A = A + multiplicand. b. If the last two bits of Q and Q0 are “00” or “11”, do nothing.Here’s the detailed process:
   • Step 1: Q0 = 0 A = 10101 Q = 01101
   • Step 2: Shift right Q and Q0. Q0 = LSB of Q, then shift right A. A = 11010 Q = 00110 Q0 = 1
   • Step 3: Since Q0 = 1, we perform A = A + multiplicand. A = 11010 + 10101 = 1011 (in 5 bits) Shift right A and Q. A = 1101 Q = 00011 Q0 = 0
   • Step 4: Since Q0 = 0, do nothing. Shift right A and Q. A = 1110 Q = 00001 Q0 = 1
   • Step 5: Since Q0 = 1, we perform A = A + multiplicand. A = 1110 + 10101 = 100111 (in 6 bits) Shift right A and Q. A = 11001 Q = 00000 Q0 = 0
4. After all iterations, concatenate Q and A to get the result.Result = 00000 11001

The result in binary is 11001, which represents -247 in decimal. Therefore, (-19) * (+13) = -247.

20. Write an assembly language program that subtract two 16 bits number and store result in memory location 2500H.

Ans: Below is a simple assembly language program written for the Intel 8086 microprocessor architecture that subtracts two 16-bit numbers and stores the result in memory location 2500H:

.model small
.stack 100h

.data
num1 dw 1234h   ; First 16-bit number (example value)
num2 dw 5678h   ; Second 16-bit number (example value)

.code
main proc
    mov ax, @data   ; Load the data segment address into AX
    mov ds, ax      ; Initialize DS with the data segment address
    
    mov ax, num1    ; Load the first number into AX
    sub ax, num2    ; Subtract the second number from AX
    
    mov bx, 2500h   ; Load the memory address 2500H into BX
    mov [bx], ax    ; Store the result in memory location 2500H
    
    mov ah, 4Ch     ; Set the exit code for DOS termination
    int 21h         ; Call the DOS service to terminate the program
main endp
end main

Group “D”

Comprehensive answer questions:

21. Draw the flowchart of Non-restoring division algorithm. Perform 11/3 by using Non-restoring division algorithm.

Ans: The non-restoring division algorithm is more complex as compared to the restoring division algorithm. But when we implement this algorithm in hardware, it has an advantage, i.e., it contains only one decision and addition/subtraction per quotient bit.

the non-restoring division algorithm to perform the division 11/3.

Here are the steps:

Step 1: Initialize

Dividend (D) = 11 (binary 1011) Divisor (d) = 3 (binary 0011)

Step 2: Determine the sign of the quotient.

Since both dividend and divisor are positive, the quotient will be positive.

Step 3: Normalize the divisor.

Since the divisor is 3, which is less than 8 (2^3), we can shift it left by 3 bits. So, the normalized divisor becomes 1100.

Step 4: Initialize the register (Q) and accumulator (A) with 0s.

Q = 0000 (4 bits) A = 0000 (4 bits)

Step 5: Perform the non-restoring division algorithm.

For each iteration:

• Shift left A and Q by one bit.
• Subtract the normalized divisor from A.
  • If the result is negative, set Q0 = 1 and add the normalized divisor back to A.
  • If the result is non-negative, set Q0 = 0.

Iteration 1: A = 0000 Q = 0000 Subtract 1100 from A: A = 0000 – 1100 = 1100 (negative) Since the result is negative, set Q0 = 1 and add 1100 back to A: A = 1100 Shift left A and Q: A = 11000, Q = 0001

Iteration 2: A = 1100 Q = 0001 Subtract 1100 from A: A = 1100 – 1100 = 0000 (non-negative) Since the result is non-negative, set Q0 = 0. Shift left A and Q: A = 00000, Q = 0010

Iteration 3: A = 0000 Q = 0010 Subtract 1100 from A: A = 0000 – 1100 = 1100 (negative) Since the result is negative, set Q0 = 1 and add 1100 back to A: A = 1100 Shift left A and Q: A = 11000, Q = 0100

Iteration 4: A = 1100 Q = 0100 Subtract 1100 from A: A = 1100 – 1100 = 0000 (non-negative) Since the result is non-negative, set Q0 = 0. Shift left A and Q: A = 00000, Q = 1000

Now, the division process stops as all bits of the quotient have been computed.

Step 6: Interpret the result.

The quotient (Q) is 1000 in binary, which is 8 in decimal.

So, 11 divided by 3 is 8 with a remainder of 11 – (3 * 8) = 11 – 24 = -13.

Thus, the result is Q = 8 and R = -13.

22. Draw the architecture of Intel 8085 microprocessor and explain each part in details.

Ans: The 8085 microprocessor is an 8-bit microprocessor that was developed by Intel in the mid-1970s. It was widely used in the early days of personal computing and was a popular choice for hobbyists and enthusiasts due to its simplicity and ease of use. The architecture of the 8085 microprocessor consists of several key components, including the accumulator, registers, program counter, stack pointer, instruction register, flags register, data bus, address bus, and control bus.

8085 consists of the following functional units −

Accumulator:

It is an 8-bit register used to perform arithmetic, logical, I/O & LOAD/STORE operations. It is connected to internal data bus & ALU.

Arithmetic and logic unit:

As the name suggests, it performs arithmetic and logical operations like Addition, Subtraction, AND, OR, etc. on 8-bit data.

General purpose register:

There are 6 general purpose registers in 8085 processor, i.e. B, C, D, E, H & L. Each register can hold 8-bit data.

These registers can work in pair to hold 16-bit data and their pairing combination is like B-C, D-E & H-L.

Program counter:

It is a 16-bit register used to store the memory address location of the next instruction to be executed. Microprocessor increments the program whenever an instruction is being executed, so that the program counter points to the memory address of the next instruction that is going to be executed.

Stack pointer:

It is also a 16-bit register works like stack, which is always incremented/decremented by 2 during push & pop operations.

Temporary register:

It is an 8-bit register, which holds the temporary data of arithmetic and logical operations.

Flag register:

It is an 8-bit register having five 1-bit flip-flops, which holds either 0 or 1 depending upon the result stored in the accumulator.

These are the set of 5 flip-flops −

• Sign (S)
• Zero (Z)
• Auxiliary Carry (AC)
• Parity (P)
• Carry (C)

Instruction register and decoder:

It is an 8-bit register. When an instruction is fetched from memory then it is stored in the Instruction register. Instruction decoder decodes the information present in the Instruction register.

Timing and control unit:

It provides timing and control signal to the microprocessor to perform operations. Following are the timing and control signals, which control external and internal circuits −

• Control Signals: READY, RD’, WR’, ALE
• Status Signals: S0, S1, IO/M’
• DMA Signals: HOLD, HLDA
• RESET Signals: RESET IN, RESET OUT

Interrupt control:

As the name suggests it controls the interrupts during a process. When a microprocessor is executing a main program and whenever an interrupt occurs, the microprocessor shifts the control from the main program to process the incoming request. After the request is completed, the control goes back to the main program.

There are 5 interrupt signals in 8085 microprocessor: INTR, RST 7.5, RST 6.5, RST 5.5, TRAP.

Serial Input/output control:

It controls the serial data communication by using these two instructions: SID (Serial input data) and SOD (Serial output data).

Address buffer and address-data buffer:

The content stored in the stack pointer and program counter is loaded into the address buffer and address-data buffer to communicate with the CPU. The memory and I/O chips are connected to these buses; the CPU can exchange the desired data with the memory and I/O chips.

Address bus and data bus:

Data bus carries the data to be stored. It is bidirectional, whereas address bus carries the location to where it should be stored and it is unidirectional. It is used to transfer the data & Address I/O devices.