Model Question And Solution 2015

Group ” A”

Brief Answer Questions:

1. Define the term normalization with respect to a floating point numbers.

Ans: Normalization, in the context of floating-point numbers, refers to the process of adjusting the representation of a number to ensure that the leading digit (or digits) of the significand (mantissa) is within a specified range, typically between 1 and the base of the number system, thereby maximizing precision and facilitating arithmetic operations.

2. Write down the symbolic designation of a shift micro-operation where the shifting is carried out without loss of information.

Ans: The symbolic designation of a shift micro-operation where the shifting is carried out without loss of information is often represented as Si​, where i denotes the number of shift positions.

3. How I/O instruction is identified in a basic computer?

Ans: I/O instruction is identified in a basic computer by specific opcodes reserved for Input/Output operations in the instruction set architecture.

4. Make distinction between RISC and CISC architecture.

Ans: The distinction between RISC and CISC architecture.

CISC.

1. CISC architectures typically have a complex instruction set with a large variety of instructions, some of which may perform complex operations or access memory directly.
2. In CISC architectures, instructions may vary in length and complexity, and a single instruction may perform multiple operations or address multiple memory locations

RISC:

1. RISC architectures have a reduced and simplified instruction set with fewer instructions, each performing a simple and well-defined operation.
2. RISC architectures emphasize simple instructions that execute quickly. Each instruction typically performs only one operation, making instruction decoding simpler and more efficient.

5. Write down the uses of sequencer in a microprogrammed control organization.

Ans: The uses of sequencer in a microprogrammed control organization are:

• Microinstruction Sequencing.
• Control Flow Management.
• Interrupt Handling.
• Exception Handling.
• Microinstruction Pipelining.

6. How is effective address is calculated in indexed register addressing mode?

Ans: The effective address is calculated in indexed register addressing mode are as followed:

• Load Base Register.
• Load Displacement.
• Addition.
• Result.

7. List solutions to control hazards.

Ans: The solutions to control hazards are as followed:

• Stall.
• Prediction.
• Dynamic Branch Prediction.
• Reordering Instructions.

8. What is the disadvantage of programmed I/O?

Ans: The disadvantage of programmed I/O are:

• High CPU Utilization.
• Slow Data Transfer.
• Limited Scalability.
• Processor Dependency.
• Inefficiency in Multitasking Environments.

9. Differentiate between logical address and virtual address.

Ans: The difference between logical address and virtual address are:

10. Define associative memory.

Ans: Associative memory, also known as content-addressable memory (CAM), is a type of computer memory architecture that allows data retrieval based on its content rather than a specific memory address

Group “B”

Short Answer Questions:

11. The 4-bit register A,B,C and D initially have the following values:

A=0010 ,B=0111 ,C=1000 ,D=1111

Determine the 4-bit values in each register after the execution of the following sequence of micro-operations.

A ← A+C

C ← C^D,D-D+1

A ← A-B

Ans:

Let’s go through the sequence of micro-operations step by step:

A ← A + C:
A = 0010
C = 1000
A + C = 1010 (2 + 8 = 10 in decimal)
So, after this operation, A becomes 1010.
C ← C ^ D, D – D + 1:
C = 1000
D = 1111
C ^ D = 0111 (exclusive OR operation)
D – D + 1 = 0001 (subtract D from itself and then add 1)
So, after this operation, C becomes 0111, and D becomes 0001.
A ← A – B:
A = 1010
B = 0111
A – B = 1010 – 0111 = 0011 (10 – 7 = 3 in decimal)
So, after this operation, A becomes 0011.
So, after the execution of the given sequence of micro-operations:

A = 0011
B = 0111
C = 0111
D = 0001

12. Write a program to take two integers and display them.

Ans: Here’s a simple assembly language program in x86 syntax that takes two integers as input and displays them in registers:

section .data
    prompt1 db 'Enter first integer: ', 0
    prompt2 db 'Enter second integer: ', 0
    format db '%d', 0

section .bss
    num1 resd 1
    num2 resd 1

section .text
    extern printf, scanf

global main
main:
    ; Prompt user for the first integer
    push prompt1
    call printf
    add esp, 4

    ; Read the first integer from user input
    push num1
    push format
    call scanf
    add esp, 8

    ; Prompt user for the second integer
    push prompt2
    call printf
    add esp, 4

    ; Read the second integer from user input
    push num2
    push format
    call scanf
    add esp, 8

    ; Display the integers in registers
    mov eax, [num1]
    mov ebx, [num2]

    ; Display the first integer
    push eax
    push format
    call printf
    add esp, 8

    ; Display the second integer
    push ebx
    push format
    call printf
    add esp, 8

    ; Exit the program
    mov eax, 0
    ret

13. Time taken to complete a task in conventional machine is 45ns. In pipelined machine, one task is divided into 5 segments and each sub-operation takes 10ns. Calculated pipeline speed up for 50 tasks and infinite tasks.

Ans: To calculate the speedup achieved by pipelining, we need to understand how pipelining affects task completion time.

In a conventional machine, tasks are completed sequentially, with no overlap between tasks. So, if one task takes 45ns, then 50 tasks would take (50 \times 45) ns.

In a pipelined machine, tasks are divided into multiple stages, and different stages of different tasks can be executed concurrently. In this case, the task is divided into 5 segments, each taking 10ns. Therefore, the throughput of the pipelined machine can be significantly higher.

Let’s calculate the time taken to complete 50 tasks in the pipelined machine:

Each task is divided into 5 segments, and each segment takes 10ns. So, the time taken for one task to complete in the pipelined machine is (5 \times 10) ns = 50 ns.

Since different tasks can overlap in a pipelined machine, the total time to complete 50 tasks in the pipelined machine would still be 50ns, regardless of the number of tasks.

Now, let’s calculate the speedup:

For 50 tasks:
Conventional machine time: (50 \times 45) ns = 2250 ns
Pipelined machine time: 50 ns

Speedup = Conventional machine time / Pipelined machine time
Speedup = (2250 {ns} / 50 {ns} = 45)

For infinite tasks, the speedup can be calculated as follows:

In a pipelined machine, since tasks can overlap and the machine can keep working without idle time, the time taken to complete tasks remains constant, regardless of the number of tasks. So, for infinite tasks, the speedup would be infinite, indicating that the pipelined machine can theoretically process an infinite number of tasks in the same time it takes to complete one task.

14. Consider the following memory and the instruction LDA 250:

Write the value loaded into AC when the addressing mode is

a) Indirect b) Register Indirect c) Immediate d) Direct

Ans:

15. Multiply +15 by -5 using booth algorithm.

Ans: To multiply numbers using Booth’s algorithm, we represent the numbers in binary and then perform a series of addition and shifting operations according to the algorithm. Here’s how you can multiply +15 and -5 using Booth’s algorithm:

1. Represent both numbers in binary: +15 = 01111 -5 = 1011 (2’s complement of 5, since we’re representing negative numbers in binary)
2. Extend the length of the multiplier to match the number of bits required to represent both numbers. Since we’re multiplying a 5-bit number by another 5-bit number, no extension is needed.
3. Perform Booth’s algorithm:Initial: A = 01111 (Multiplier) Q = 1011 (Multiplicand) Q(-1) = 0 (Initial value)Iteration 1:
   • Since Q(-1) = 0, do nothing.
   Iteration 2:
   • Shift right (Q, Q(-1), A): A = 00111 Q = 1101 Q(-1) = 1
   • Subtract Q from A: A = 00111 – 00000 – 1101 (2’s complement of Q) = 00111 + 0011 = 01110
   Iteration 3:
   • Shift right (Q, Q(-1), A): A = 00011 Q = 1110 Q(-1) = 0
   • Subtract Q from A: A = 00011 – 01110 (2’s complement of Q) = 00011 + 10010 = 10101
   Iteration 4:
   • Shift right (Q, Q(-1), A): A = 00001 Q = 1111 Q(-1) = 0
   • Subtract Q from A: A = 00001 – 01111 (2’s complement of Q) = 00001 + 10001 = 10010
   Final result: A = 10010 (Binary) = -75 (Decimal)

So, +15 multiplied by -5 using Booth’s algorithm results in -75.

Group “C”

Comprehensive Answer Questions:

16. Explain how data is transferred using handshaking methods ? Explain interrupt cycle of Basic Computer.

Ans: Handshaking methods are protocols used in communication systems to establish and maintain a connection between two entities, such as devices or systems. These methods involve a series of predefined steps or signals exchanged between the sender and receiver to synchronize their communication and ensure reliable data transfer.

Here’s an explanation of how data is transferred using handshaking methods:

1. Initialization: The process begins with an initialization phase where both the sender and receiver prepare for communication. This may involve setting up parameters such as data rates, protocols, and addressing schemes.
2. Request-Response Sequence: In many handshaking protocols, the sender initiates communication by sending a request or a signal to the receiver. The receiver then responds to this request, indicating its readiness to receive or send data.
3. Synchronization: Handshaking methods ensure synchronization between the sender and receiver. This synchronization ensures that both parties are operating at the same pace and are ready to exchange data. Synchronization may involve agreeing on the timing, data format, and flow control mechanisms.
4. Acknowledgment: After receiving data, the receiver sends an acknowledgment signal back to the sender. This acknowledgment confirms that the data has been received successfully and indicates readiness for the next data transfer.
5. Error Handling: Handshaking methods often include error detection and correction mechanisms to ensure data integrity. If errors are detected during transmission, the sender and receiver may engage in error recovery procedures, such as retransmission of data or requesting retransmission of specific segments.
6. Termination: Once the data transfer is complete, the sender and receiver may perform termination procedures to end the communication session gracefully. This may involve exchanging termination signals or closing connections.

Handshaking methods are crucial for ensuring reliable and orderly communication between devices in various systems, including computer networks, serial communication links, and digital interfaces.

In the Basic Computer architecture, the interrupt cycle allows the computer to handle external events or requests for service that occur asynchronously with the execution of the main program. Here’s an interrupt cycle of Basic Computer and they are:

1. Normal Execution: The Basic Computer primarily executes instructions in a sequential manner, fetching instructions from memory, decoding them, executing them, and then moving on to the next instruction.
2. Interrupt Occurrence: At any point during the execution of the main program, an external event or request for service may occur. This could be a hardware interrupt, such as a timer reaching zero, a keyboard input, or a signal from an I/O device indicating that data is ready for transfer.
3. Interrupt Signal: When an interrupt occurs, the external device sends an interrupt signal to the Basic Computer. This signal interrupts the normal flow of execution and causes the computer to temporarily suspend the execution of the current program.
4. Interrupt Acknowledgment: Upon receiving the interrupt signal, the Basic Computer enters the interrupt cycle. The first step in this cycle is to acknowledge the interrupt. This acknowledgment typically involves saving the address of the next instruction to be executed (the return address) and transferring control to a predefined location in memory called the interrupt vector or interrupt handler.
5. Interrupt Service Routine (ISR): The interrupt vector points to the starting address of an Interrupt Service Routine (ISR) or Interrupt Handler. This routine is a special section of code designed to handle the specific interrupt that occurred.
6. Interrupt Service: The ISR executes to service the interrupt. Once the ISR completes its tasks, it typically restores the saved state of the interrupted program, including the return address, and returns control to the main program.
7. Resumption of Normal Execution: After the interrupt has been serviced and the ISR has returned control to the main program, the Basic Computer resumes normal execution from the point where it was interrupted.

The interrupt cycle allows the Basic Computer to handle asynchronous events and respond promptly to external requests while maintaining the integrity and continuity of the main program execution.

17. Explain any two interconnection structures for a multi-processor. Explain cache mapping techniques.

Ans: The two interconnection structures for a multi-processor are as given below:

1. Bus-Based Interconnection: In a bus-based interconnection structure, all processors share a common communication bus. This bus serves as the main communication medium through which processors can exchange data and coordinate their activities. Each processor connects to the bus via a bus interface unit. When a processor wants to communicate with another processor or access shared memory, it sends its request onto the bus. This is because all communication between processors must pass through the same bus, leading to potential congestion and contention.
2. Crossbar Interconnection: In a crossbar interconnection structure, multiple processors and memory modules are interconnected using a grid-like network of switches called a crossbar. Each switch in the crossbar connects one input port to one output port, allowing for simultaneous communication between multiple pairs of processors and memory modules. Crossbar interconnects provide full interconnection between all processors and memory modules, offering high bandwidth and low latency.

There are various cache mapping techniques and some of them are as:

1. Direct Mapping:

• Each memory block is mapped to exactly one cache line.
• The mapping is determined by a modulo function, which maps memory addresses to specific cache lines.
• Simple and easy to implement but may lead to cache conflicts.

2. Fully Associative Mapping:

• Each memory block can be placed in any cache line.
• No restrictions on the placement of memory blocks.
• Offers maximum flexibility and minimizes cache conflicts but requires complex hardware for searching cache contents.

3. K-way Set-Associative Mapping:

• Combines aspects of both direct mapping and fully associative mapping.
• Memory is divided into a number of sets, and each set contains multiple cache lines.
• Each memory block can be mapped to any cache line within its corresponding set.
• Allows for more flexibility and reduces the chance of cache conflicts compared to direct mapping.