Model Question And Solution 2022

Group “A”

Brief Answer Questions:

1. How the floating point numbers are represented ?

Ans: Floating-point numbers are typically represented using a standardized format known as the floating-point representation.

2. What is Instruction Set Completeness?

Ans: Instruction Set Completeness refers to the extent to which an instruction set architecture (ISA) provides a comprehensive and sufficient set of instructions to perform all necessary operations and tasks required by software applications and programmers.

3. If (R1 =1011), what will be its value after arithmetic right shift and arithmetic left shift operation?

Ans: If (R1 =1011), then its value after arithmetic right shift and arithmetic left shift operation 1101 and 0110 respectively.

4. Write down the micro operation for instruction fetch cycle.

Ans: The micro operation for instruction fetch cycle are:

• Memory Address Generation.
• Memory Read.
• Data Transfer.
• Program Counter Update.

5. How the resource conflict problem is solved in pipelining processing?

Ans: The resource conflict problem is solved in pipelining processing are:

• Resource Partitioning.
• Resource Scheduling.
• Compiler Optimization.
• Resource Duplication.

6. What is the problem of programmed I/O interface?

Ans: The problem of programmed I/O interface are:

• CPU Overhead.
• Slow Data Transfer.
• Inefficiency.

7. What is the importance of I/O interface?

Ans: The importance of I/O interface are:

• Resource Management.
• Data Transfer.
• Connectivity.
• Device Control and Configuration.

8. Define locality of reference principle.

Ans: The locality of reference principle, also known as the principle of locality, is a fundamental concept in computer science and computer architecture that describes the tendency of programs to access a relatively small subset of memory locations or data at any given time.

9. What is cache coherency problem?

Ans: The cache coherency problem refers to the challenge of maintaining consistency and synchronization of data stored in multiple cache memories within a multiprocessor system

10. List out any two characteristics of multiplication system.

Ans: The two characteristics of multiplication system are:

• Algorithmic Efficiency.
• Parallelism.

Group ” B”

Exercise Problems:

11. Write a program to input two numbers and display the sum.

Ans:

12. Perform the operation -8X+24 by using signed magnitude multiplication algorithm.

Ans:

13. A computer have cache access time of 50 ns and main memory access time of 1200 ns. 90% of the required data are found in a cache memory . Calculate the average memory access time.

Ans: SOLUTION:

To calculate the average memory access time (AMAT), we use the following formula:

AMAT=Hit time +Miss rate × Miss penalty.

Where:

• Hit time is the access time when the data is found in the cache.
• Miss rate is the probability that a memory access results in a cache miss.
• Miss penalty is the time it takes to fetch data from the main memory when there is a cache miss.

Given:

• Cache access time (Hit time): 50 ns
• Main memory access time (Miss penalty): 1200 ns
• Hit rate (percentage of data found in cache): 90% (0.90)
• Miss rate = 1 – Hit rate = 1 – 0.90 = 0.10

Now, let’s calculate the average memory access time:

AMAT=Hit time +Miss rate × Miss penalty

AMAT=50ns+0.10×1200ns

AMAT=50ns+120ns

AMAT=170ns

Therefore, the average memory access time is 170 nanoseconds.

14. Write a modular program to implement the following expression using three and zero address instructions.

X = (A+B) *[(C*D) +F]

Where capital alphabet represents the memory label.

Ans: Implement the given expression using both three-address and zero-address instructions:

1. Three-Address Instructions:

2. Zero-Address Instructions:

These are simplified examples of assembly-like code that would need to be translated into the appropriate machine code for the target architecture. Additionally, they assume the existence of suitable instructions and registers or a stack for storing intermediate values.

15. Design pipeline configuration to perform the arithmetic operation (A_i +B_i) * (C_i +D_i) with streams of numbers from i-1 through 6.

Ans:

Group “C”

Comprehensive Answer Questions:

16. Explain Instruction Cycle with the help of a flowchart.

Ans: In a Computer architecture, the execution of instructions typically follows a fetch-decode-execute cycle, where instructions are fetched from memory, decoded to determine the operation to be performed, and then executed by the CPU. Here’s a simplified explanation of how instructions are executed in a basic computer:

1. Fetch Phase:
   • The CPU fetches the next instruction from memory using the program counter (PC), which contains the address of the next instruction to be executed.
   • The instruction is loaded into the instruction register (IR) for decoding.
2. Decode Phase:
   • The CPU decodes the instruction in the instruction register to determine the operation to be performed and the operands involved.
   • Control signals are generated based on the decoded instruction to configure the CPU’s control unit and data path for the upcoming operation.
3. Execute Phase:
   • The CPU executes the decoded instruction by performing the specified operation, which may involve reading from or writing to registers, performing arithmetic or logical operations, accessing memory, or transferring control to another part of the program.
   • After execution, the program counter (PC) is updated to point to the next instruction in memory, and the process repeats.

17. Illustrate and explain the working principle of DMA.

Ans: Direct Memory Access (DMA) is a technique used to transfer data between peripheral devices and memory without involving the CPU. DMA controllers manage these data transfers independently, allowing the CPU to focus on other tasks while data is transferred in the background.

1. Initialization: The CPU initializes the DMA controller by providing it with parameters such as the source and destination addresses, transfer length, and transfer direction.
2. Arbitration: If multiple devices request DMA access simultaneously, the DMA controller arbitrates between them based on priority or a predetermined scheme.
3. Bus Request: When the DMA controller needs access to the system bus, it sends a bus request signal to the CPU.
4. Bus Grant: If the CPU grants the bus request, the DMA controller gains control of the bus and proceeds with the data transfer.
5. Data Transfer: The DMA controller transfers data directly between the peripheral devices and memory without CPU intervention. This process continues until the transfer is complete or until the DMA controller releases control of the bus.
6. Completion: Once the data transfer is finished, the DMA controller releases control of the bus and may generate an interrupt to inform the CPU about the completion of the transfer.

Working Principle:

1. CPU Initialization: The CPU sets up the DMA controller by providing it with the necessary parameters, such as the source and destination addresses and the transfer length.
2. Bus Arbitration: The DMA controller requests control of the system bus from the CPU. If the CPU grants the request, the DMA controller gains control of the bus.
3. Data Transfer: With control of the bus, the DMA controller initiates the data transfer between the peripheral devices and memory. It reads data from the source device, writes it to the destination location in memory, and updates the memory address pointers as needed.
4. Bus Release: Once the data transfer is complete, the DMA controller releases control of the bus, allowing the CPU to regain control.
5. Interrupt Generation: Optionally, the DMA controller can generate an interrupt signal to inform the CPU that the data transfer has been completed. This allows the CPU to perform any necessary follow-up actions, such as processing the transferred data or initiating additional operations.

By using DMA, the CPU can offload data transfer tasks to the DMA controller, improving overall system efficiency and allowing the CPU to focus on other tasks simultaneously.