Model Questions and Solutions BIM 3rd Semester

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Model Question And Solution 2016

Ans: The importance of complement in digital computers are:

  • Arithmetic operations.
  • Logic operations
  • Data representation.


Ans: The purpose of location counter in assembler are:

  • Memory Allocation.
  • Instruction Encoding.
  • Symbol Resolution.
  • Code Relocation.
  • Error Detection.

Ans: 12 bits bits are required to address 4096 bytes of memory.

Ans: Dynamic microprogramming is a technique used in microprocessor design where the microinstructions, which control the operation of the microprocessor, are stored in a writable control store or control memory.

Ans: The purpose of strobe pulse in asynchronous data transfer are:

  • Data Validity.
  • Timing Control.
  • Noise Immunity.

Ans: The major difficulties that cause the instruction pipeline to deviation from normal operation are:

  • Data Hazards.
  • Resource Conflicts.
  • Branch Prediction Failures.
  • Branch Prediction Failures.
  • Interrupts and Exceptions

Ans: The principle behind the implementation of cache memory are:

  • Temporal Locality.
  • Cache Hierarchy.
  • Cache Replacement Policies.

Ans: The function of IOP are:

  • Interface with Peripheral Devices.
  • Data Transfer Control.
  • Data Buffering.
  • Device Management.

Ans: A critical section in computer programming is a part of a multi-process program that must not be concurrently executed by more than one process.




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Ans: An associative memory can be considered as a memory unit whose stored data can be identified for access by the content of the data itself rather than by an address or memory location. In associative memory, the data is stored along with associated tags or keys, and retrieval is performed by specifying the content (or a portion of it) rather than a specific memory address.

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AMAT(Average Memory Access Time) =Hit time +Miss rate× Miss penalty


  • Hit time is the access time for cache memory.
  • Miss rate is 1−Hit ratio1−Hit ratio, which represents the probability of a cache miss.
  • Miss penalty is the additional time required when a cache miss occurs, which is the access time for RAM.


  • Hit time = 200 ns (cache access time)
  • Miss rate = 1 – Hit ratio = 1 – 0.90 = 0.10
  • Miss penalty = 2000 ns (RAM access time)

Now, let’s plug these values into the formula:

AMAT=200 ns+0.10×2000 ns

AMAT=200 ns+0.10×2000 ns

AMAT=200 ns+200 ns

AMAT=400 ns

So, the average memory access time (AMAT) is 400 ns.

Ans: A common bus system, also known as a shared bus or system bus, is a communication pathway shared by multiple components within a computer system. Common bus systems play a crucial role in facilitating communication and data exchange between components within a computer system, enabling efficient operation and coordination of system resources.

The advantage of common bus system are:

  1. Simplicity: Common bus systems have a straightforward design with a single set of communication lines shared by all components. This simplicity reduces the complexity of the system architecture, making it easier to design, implement, and troubleshoot.
  2. Cost-Effectiveness: Implementing a common bus system is typically more cost-effective compared to alternative architectures such as point-to-point or crossbar systems. It requires fewer interconnects and routing resources, resulting in lower hardware costs.
  3. Flexibility: A common bus system allows for flexible connectivity between different components within the system. New devices or modules can be easily added to the bus without requiring significant changes to the overall system architecture, facilitating system expansion and scalability.
  4. Resource Sharing: With a common bus system, multiple devices can share resources such as memory or I/O interfaces. This promotes efficient resource utilization and maximizes system throughput by avoiding resource duplication.
  5. Ease of Troubleshooting: Troubleshooting and debugging in common bus systems are simplified because all communication between components occurs over the same bus. This makes it easier to monitor and analyze bus transactions, identify communication issues, and diagnose faults or errors within the system.
  6. Standardization: Common bus systems often adhere to standard protocols and interfaces, making them compatible with a wide range of devices and peripherals.

Vector processing, also known as vectorization, is a type of parallel computing paradigm that involves performing the same operation on multiple data elements simultaneously. In vector processing, a single instruction is applied to a group of data elements, known as a vector, in a coordinated and efficient manner.

Ans: An interrupt tells the CPU that the device needs attention and that the CPU should stop any current activity and respond to the device. If the CPU is not performing a task that has higher priority than the priority of the interrupt, then the CPU suspends the current thread. Here’s are priorities interrupt handled are :

  1. Interrupt Prioritization: Each interrupt source in the system is assigned a priority level, often represented by a numerical value or priority code. Interrupts with higher priority levels are given precedence over those with lower priority levels.
  2. Interrupt Masking: The CPU’s interrupt controller or interrupt handling mechanism may include provisions for masking interrupts based on their priority levels. This means that interrupts with lower priority levels may be temporarily disabled or masked when higher-priority interrupts occur, ensuring that critical interrupts are serviced promptly.
  3. Priority-Based Interrupt Handling: When multiple interrupts are pending, the CPU’s interrupt handling routine selects the highest-priority interrupt that is currently active and services it first. Once the highest-priority interrupt is processed, the CPU may proceed to handle lower-priority interrupts in their respective order.
  4. Nested Interrupts: In systems that support nested interrupts, higher-priority interrupts can preempt the execution of lower-priority interrupt service routines. This allows for more efficient handling of time-critical events and ensures that higher-priority interrupts are not delayed by lower-priority interrupt processing.
  5. Interrupt Service Routine (ISR) Overhead: Interrupt service routines should be designed to execute quickly and efficiently, especially for high-priority interrupts. Minimizing the overhead of ISR execution helps reduce interrupt latency and ensures timely response to critical events.
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Instruction set completeness, refers to the extent to which an instruction set architecture (ISA) provides a comprehensive set of instructions that can perform a wide range of tasks and operations required by software applications.

In summary, instruction set completeness is an important consideration in ISA design, as it directly impacts the expressiveness, efficiency, and versatility of the architecture for software development and execution. A more complete instruction set provides greater flexibility and capabilities for implementing diverse algorithms and applications.

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