Model Questions and Solutions BIM 3rd Semester

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Model Question And Solution 2017

Ans: The advantages of normalized floating point number are:

  • Increased Precision.
  • Wider Dynamic Range.
  • Simplified Arithmetic Operations.
  • Compatibility and Portability.

Ans: Control data register in micro-programmed control organization is called pipeline register because  it allows the execution of the microoperations specified by the control word simultaneously with the generation of the next microinstruction.

Ans: The different technique used to achieve parallel processing are mentioned below:

  • Instruction-Level Parallelism (ILP).
  • Thread-Level Parallelism (TLP).
  • Data-Level Parallelism (DLP).
  • Task-Level Parallelism (TLP).
  • Parallel Architectures.
  • Data Parallelism.
  • Pipeline Processing.

Ans: The difference between address space and memory space are :

AspectsAddress SpaceMemory Space
DefinitionAddress space refers to the range of addresses that a process can use to access memory. Memory space refers to the actual physical memory capacity available in a computer system, typically measured in bytes or units of memory storage.
RepresentationIt is represented as a range of addresses, typically expressed in hexadecimal or binary format.It is represented as a quantity of memory storage, typically measured in bytes or units such as kilobytes (KB), megabytes (MB), gigabytes (GB), etc.

Ans: Interrupt-initiated I/O is preferable to programmed I/O because it allows the CPU to perform other tasks while waiting for I/O operations to complete, improving system efficiency and responsiveness.

Ans: Peripherals are connected to computers through interfaces because to facilitate communication and ensure compatibility between the diverse range of devices and the computer system.

Ans: The microinstruction format of a basic computer typically includes fields for specifying the microoperation to be performed, control signals to activate various hardware components, and addressing modes for accessing operands or memory locations.

Ans: Hierarchy of memory is maintained to achieve efficient operations by organizing the memory to reduce access time while speeding up operations.

Ans: The difference between vector and array processor are:

AspectsVector ProcessorArray Processor
Basic OperationVector processors typically use specialized vector instructions to perform parallel computations on large sets of data elements in a coordinated manner.Array processors often consist of multiple processing elements or cores that work in parallel to perform computations on different parts of the array.
Memory AccessThey perform bulk memory transfers between memory and vector registers to load/store vector data efficiently.In shared memory architectures, processing elements access a common memory space, allowing for more flexible data sharing and communication between processing elements.

Ans: Cache memory is a chip-based computer component that makes retrieving data from the computer’s memory more efficient. It acts as a temporary storage area that the computer’s processor can retrieve data from easily.


Ans: In a Computer architecture, the execution of instructions typically follows a fetch-decode-execute cycle, where instructions are fetched from memory, decoded to determine the operation to be performed, and then executed by the CPU. Here’s a simplified explanation of how instructions are executed in a basic computer:

  1. Fetch Phase:
    • The CPU fetches the next instruction from memory using the program counter (PC), which contains the address of the next instruction to be executed.
    • The instruction is loaded into the instruction register (IR) for decoding.
  2. Decode Phase:
    • The CPU decodes the instruction in the instruction register to determine the operation to be performed and the operands involved.
    • Control signals are generated based on the decoded instruction to configure the CPU’s control unit and data path for the upcoming operation.
  3. Execute Phase:
    • The CPU executes the decoded instruction by performing the specified operation, which may involve reading from or writing to registers, performing arithmetic or logical operations, accessing memory, or transferring control to another part of the program.
    • After execution, the program counter (PC) is updated to point to the next instruction in memory, and the process repeats.
image 21

Ans: Given:

The time delay of the four segments in the pipeline system are t1 =30ns, t2 =35ns,t3 =20ns and t4=45ns.

delay time d=4ns

For the pipeline system:

Total time Tp​ taken to process 100 tasks = t1​+t2​+t3​+t4​+(100−1)×(t1​+t2​+t3​+t4​+d)

For the conventional system:

Total time Tc​ taken to process 100 tasks = 100×(t1​+t2​+t3​+t4​)

Now, we can calculate the total time taken by each system:

For the pipeline system:





Tp​=13396 ns

For the conventional system:




Tc​=13000 ns

Now, we can calculate the speedup ratio:

Speedup ratio=Tc/​Tp​​

Speedup ratio=13000/​13396

Speedup ratio≈0.9696

So, the speedup ratio of the pipeline system over the equivalent conventional system is approximately 0.9696.



Ans: CPU organizations refer to the architectural designs and structures of central processing units (CPUs) used in computer systems. Different CPU organizations offer varying levels of complexity, performance, and capabilities. Some common CPU organizations include:

  1. Single-Core CPU:
    • A single-core CPU consists of a single processing core that executes instructions sequentially.
    • It can perform one instruction at a time and is limited in its ability to execute tasks concurrently.
    • Single-core CPUs are commonly found in simple embedded systems, low-power devices, and older computing devices.
  2. Multi-Core CPU:
    • A multi-core CPU contains multiple processing cores integrated onto a single chip.
    • Each core operates independently and can execute instructions concurrently, enabling parallel processing of tasks.
    • Multi-core CPUs offer improved performance and multitasking capabilities compared to single-core CPUs, making them suitable for a wide range of computing applications.
  3. Symmetric Multiprocessing (SMP):
    • SMP is a CPU organization where multiple identical processing cores share a common memory and are interconnected via a system bus or interconnect fabric.
    • Each core has equal access to system resources, including memory, I/O devices, and peripherals.
    • SMP systems are designed to distribute processing tasks across multiple cores, providing scalability and improved performance for parallelizable workloads.
  4. Asymmetric Multiprocessing (AMP):
    • In AMP, different processing cores within a CPU have different roles or capabilities.
    • One core may serve as the primary or master core responsible for handling system tasks and scheduling, while other cores may be specialized for specific tasks or operate at different clock speeds.
    • AMP architectures are commonly found in embedded systems and mobile devices, where power efficiency and task specialization are important considerations.
  5. Heterogeneous Multicore CPU:
    • A heterogeneous multicore CPU combines multiple processing cores of different architectures or capabilities onto a single chip.
    • Each core may have different instruction set architectures (ISAs), microarchitectures, or specialized accelerators tailored for specific tasks (e.g., graphics processing units, AI accelerators).
    • Heterogeneous multicore CPUs offer versatility and performance optimization by leveraging a mix of processing elements suited for different types of computations.

Addressing modes define the methods used by CPUs to access operands or data during instruction execution. Different addressing modes offer flexibility and efficiency in accessing data from various sources.

Here are some common types of addressing modes along with explanations:

  1. Immediate Addressing:
    • In immediate addressing, the operand is specified directly within the instruction itself.
    • Example: MOV R1, #10 loads the immediate value 10 into register R1.
  2. Direct Addressing:
    • In direct addressing, the operand is the address of a memory location where the data resides.
    • Example: LOAD R2, 500 loads the contents of memory address 500 into register R2.
  3. Indirect Addressing:
    • In indirect addressing, the operand contains the address of a memory location, which holds the address of the actual data.
    • Example: LOAD R3, [R2] loads the contents of the memory location pointed to by the value in register R2 into register R3.
  4. Register Addressing:
    • In register addressing, the operand is the contents of a register.
    • Example: ADD R4, R5 adds the contents of register R5 to the contents of register R4.
  5. Indexed Addressing:
    • Indexed addressing involves adding an offset value to a base address to calculate the effective address of the operand.
    • Example: LOAD R6, [R7 + 100] loads the contents of the memory location at the address obtained by adding 100 to the contents of register R7 into register R6.
  6. Relative Addressing:
    • Relative addressing involves specifying the operand as an offset value relative to the current instruction pointer or program counter.
    • Example: JUMP 10 jumps to the instruction located 10 bytes ahead of the current instruction.
  7. Base-Indexed Addressing:
    • Base-indexed addressing combines base and index registers with an offset to calculate the effective address.
    • Example: LOAD R8, [R9 + R10 + 50] loads the contents of the memory location at the address obtained by adding the contents of registers R9 and R10, along with an offset of 50.
  8. Stack Addressing:
    • Stack addressing involves pushing and popping data onto and from a stack data structure.
    • Example: PUSH R11 pushes the contents of register R11 onto the stack.

Ans: A hypercube interconnection structure is a network topology commonly used in parallel computing systems. It is based on the concept of hypercubes, which are multidimensional structures that can be easily mapped onto binary numbers.

Here’s a brief explanation of hypercube interconnection structure along with its merits and demerits:


  • A hypercube interconnection structure is constructed from n-dimensional hypercubes, where each node represents a processing element (PE) or computing resource.
  • Each node is connected to log2(n) other nodes, forming a fully connected network topology.
  • Nodes communicate with each other through direct links along the edges of the hypercube, allowing for efficient message passing and data exchange.


  1. Scalability: Hypercube interconnection structures are highly scalable and can accommodate a large number of nodes without sacrificing network performance.
  2. Fault Tolerance: Hypercubes exhibit inherent fault tolerance properties, as any single node failure only affects a small portion of the network and does not disrupt communication between other nodes.
  3. Low Latency: Communication between neighboring nodes in a hypercube interconnection is direct and requires a small number of hops, resulting in low communication latency.
  4. High Bandwidth: The multiple parallel communication paths in a hypercube interconnection provide high bandwidth, enabling efficient data transfer and parallel processing.
  5. Regular Structure: Hypercube interconnections have a regular and symmetric structure, which simplifies routing algorithms, fault detection, and network management.


  1. Complex Routing: Despite their regular structure, hypercube interconnection networks require sophisticated routing algorithms to determine the optimal path for communication between nodes.
  2. Limited Connectivity: While hypercube networks provide direct connections between neighboring nodes, they may have limited connectivity compared to other interconnection topologies such as mesh or torus networks.
  3. Hardware Complexity: Implementing a hypercube interconnection network requires a significant amount of hardware resources, especially for higher-dimensional hypercubes, which may increase cost and complexity.
  4. Dimension Dependence: The performance of a hypercube interconnection is highly dependent on the dimensionality of the hypercube. Higher-dimensional hypercubes may exhibit increased communication latency and reduced fault tolerance.

Cache coherence is defined as a consistency and synchronization of data stored in different caches within a multiprocessor or multicore system. In such systems, each processor or core typically has its own cache memory to improve performance.

There are various cache mapping techniques and some of them are as:

Group 17 1
  1. Direct Mapping:
    • Each memory block is mapped to exactly one cache line.
    • The mapping is determined by a modulo function, which maps memory addresses to specific cache lines.
    • Simple and easy to implement but may lead to cache conflicts.
image 11

2. Fully Associative Mapping:

  • Each memory block can be placed in any cache line.
  • No restrictions on the placement of memory blocks.
  • Offers maximum flexibility and minimizes cache conflicts but requires complex hardware for searching cache contents.
image 5

3. K-way Set-Associative Mapping:

  • Combines aspects of both direct mapping and fully associative mapping.
  • Memory is divided into a number of sets, and each set contains multiple cache lines.
  • Each memory block can be mapped to any cache line within its corresponding set.
  • Allows for more flexibility and reduces the chance of cache conflicts compared to direct mapping.
sm 1

These mapping techniques help optimize cache performance by balancing factors such as cache access time, cache size, and complexity of cache hardware. The choice of mapping technique depends on the specific requirements and constraints of the system design.

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