Here is the explanation of RISC and CISC:
Reduced Instruction Set Computer(RISC):
RISC stands for Reduced Instruction Set Computer. It is a type of computer architecture design that emphasizes a simplified and streamlined set of instructions for the processor.
- The fundamental idea behind RISC architecture is to optimize instruction execution by providing a small, highly efficient set of instructions that can be executed in a single clock cycle.
- This contrasts with Complex Instruction Set Computing (CISC) architectures, which have a larger and more complex set of instructions.
Major Characteristics of a RISC:
» Relatively few instructions
» Relatively few addressing modes.
» Memory access limited to load and store instruction.
» All operations done within the registers of the CPU.
» Fixed-length, easily decoded instruction format.
» Single-cycle instruction execution.
» Hardwired rather than microprogrammed control.
Complex Instruction Set Computer(CISC):
CISC stands for Complex Instruction Set Computer. It represents a type of computer architecture design that features a large set of complex instructions.
- Unlike RISC (Reduced Instruction Set Computing), where the emphasis is on simplicity and executing a smaller number of instructions quickly.
- CISC architectures aim to provide a more extensive and versatile set of instructions that can perform more complex operations with a single instruction.
Major Characteristics of a CISC:
» A large number of instructions – typically from 100 to 250 instruction.
» Some instructions that perform specialized tasks and are used infrequently.
» A large variety of addressing modes – typically from 5 to 20 different modes.
» Variable-length instruction formats.
» Instructions that manipulate operands in memory.
Differences between RISC and CISC:
Here’s a tabular representation summarizing the differences between RISC and CISC architectures:
| Feature | RISC (Reduced Instruction Set Computing) | CISC (Complex Instruction Set Computing) |
|---|---|---|
| Instruction Set | Simplified, smaller instruction set | More extensive, larger instruction set |
| Instruction Complexity | Instructions perform basic operations | Instructions can perform complex operations |
| Instruction Length | Uniform length | Variable length |
| Execution Time | Generally executes instructions in fewer cycles | Some instructions may take longer to execute |
| Memory Access | Typically load/store architecture | May allow direct memory access for certain ops |
| Hardware Complexity | Simpler hardware implementation | More complex hardware required for instruction set |
| Pipelining | Well-suited for pipelining | May be more challenging to implement pipelining |
| Examples | ARM, MIPS, PowerPC | x86 (Intel, AMD), DEC VAX |
Overlapped Register Windows:
Overlapped Register Windows (ORW) is a feature found in some computer architectures, notably in some SPARC processors.
• It’s designed to improve performance by reducing the overhead of function calls and returns.
- In this organization, the RISC CPU contains 74 registers. Registers R0 to R9 are global registers that contain parameters which are common to all procedures.
- The remaining registers(R10 to R73) are divided into four windows to contain procedures A, B, C and D.
- Each window contains 10 local registers and two sets of 6 registers common to consecutive windows. Local registers contain local variables and common overlapped registers help to pass parameters between adjacent procedures without actual movement of data.
- One of the register window is activated at a time. The high registers of the calling procedure overlap the low registers of the called procedures, therefore parameters are passed from calling to called procedure easily.
For Example:
- Procedure C called procedure D. Therefore, registers R58 to R63 are common to both procedures C and D. Therefore, procedure C stores parameters for procedure D in these registers. Procedure D uses registers R64 to R73 to store the local variables.
- When procedure B returns after performing its computation, then the result from registers(R26 to R31) is transferred back to window A.
- Registers R10 to R15 are common to procedures A and D also the four windows have a circular organization.
- As R0 to R9(i.e. 10 registers) is available all procedures. Therefore, a procedure contains 32 registers while procedure it is active(which includes 10 global ,10 local, 6 low overlapping registers and 6 high overlapping registers) .
- The organization of register windows has the relationship as
- Number of global registers = g
- Number of local registers present in each window = l
- Number of registers common to two adjacent windows = c
- Number of windows = w
Then the number of registers available for each window is calculated by:
Window size = l+2c+g
The total number of registers required in the processor is:
Register file = (l + c)w+ g
For Example:
- In the above figure we have g= 10, l= 10, c= 6, w= 4, then
- the window size = 10+2×6+4 = 36 and register file size = (10+6)×4 + 10 = 74 registers.
Berkeley RISC I:
Berkeley RISC I (Reduced Instruction Set Computer) is one of the earliest examples of a RISC architecture developed at the University of California, Berkeley, in the early 1980s.
• It was primarily designed by David Patterson, Carlo H. Séquin, and their students.
• RISC I was a proof-of-concept project aimed at demonstrating the feasibility and benefits of a simplified instruction set architecture.
Instruction Set of Berkeley RISC I:
