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Priority Interrupt

Here is the key explanation of Priority Interrupt:

A priority interrupt is a system that determines the priority at which devices generating interrupt signals simultaneously should be serviced by the CPU first. High-speed transfer devices are generally given high priority, and slow devices have low priority.

• And, in case of multiple devices sending interrupt signals, the device with high priority gets the service first.

Polling is not a hardware mechanism, its a protocol in which CPU steadily checks whether the device needs attention.

Wherever device tells process unit that it desires hardware processing, in polling process unit keeps asking the I/O device whether or not it desires CPU processing.

The CPU ceaselessly check every and each device hooked up thereto for sleuthing whether or not any device desires hardware attention. Each device features a command-ready bit that indicates the standing of that device, i.e., whether or not it’s some command to be read by hardware or not. If command bit is ready one, then it’s some command to be read else if the bit is zero, then it’s no commands.

Let’s see that the difference between interrupt and polling:

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  • This method uses hardware to establish the priority of simultaneous interrupts. Deciding the interrupt priority includes the serial connection of all the devices that generate an interrupt signal. The devices are placed according to their priority such that the device having the highest priority gets placed first, followed by lower priority devices. The device with the lowest priority is found at last within the chain. In the daisy-chaining device, all devices are linked in serial form. The interrupt line request is not unusual to devices. 
  • Even if one of the devices has an interrupt signal in the low-level state, the interrupt line goes to a low-level state and allows the interrupt input within the CPU. While there’s no interrupt, the interrupt line remains in a high-level state. The CPU responds to the interrupt by allowing the interrupt acknowledge line. This signal is received via device ‘1’ at its PI input. The acknowledge signal passes to the subsequent device through PO output if tool ‘1’ isn’t asking for an interrupt.
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 There is an interrupt request line which is common to all the devices and goes into the CPU.

  • When no interrupts are pending, the line is in HIGH state. But if any of the devices raises an interrupt, it places the interrupt request line in the LOW state.
  • The CPU acknowledges this interrupt request from the line and then enables the interrupt acknowledge line in response to the request.
  • This signal is received at the PI(Priority in) input of device 1.
  • If the device has not requested the interrupt, it passes this signal to the next device through its PO(priority out) output. (PI = 1 & PO = 1)
  • However, if the device had requested the interrupt, (PI =1 & PO = 0)
    • The device consumes the acknowledge signal and block its further use by placing 0 at its PO(priority out) output.
    • The device then proceeds to place its interrupt vector address(VAD) into the data bus of CPU.
    • The device puts its interrupt request signal in HIGH state to indicate its interrupt has been taken care of.
  • If a device gets 0 at its PI input, it generates 0 at the PO output to tell other devices that acknowledge signal has been blocked. (PI = 0 & PO = 0)

Hence, the device having PI = 1 and PO = 0 is the highest priority device that is requesting an interrupt. Therefore, by daisy chain arrangement we have ensured that the highest priority interrupt gets serviced first and have established a hierarchy. The farther a device is from the first device, the lower its priority.

daisy chain priority interrupt stage

The parallel priority interrupts method uses a register whose bits are set one after the other through the interrupt signal from every device. Priority is established in step with the position of the bits inside the register. 

• Along with the interrupt register, the circuit may add a mask register whose motive is to control the status of every interrupt(interrupt signal). The mask register could be programmed for disabling lower-priority interrupts even as a higher-priority device is being serviced. Even as a higher priority device is being serviced, lower priority interrupts are disabled by the programming mask register. It could also offer a facility that permits a high-priority device to interrupt the CPU simultaneously while a lower-priority device gets service. The figure above shows the logic for deciding priority among four interrupt source systems.


Priority encoder is a combinational logic circuit used in digital electronics to prioritize multiple inputs and produce a binary output representing the highest-priority active input.

  • It’s commonly used in various applications such as interrupt handling, data multiplexing, and address encoding in microprocessors and digital systems.

The truth table of the 4-input priority encoder is shown below.

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From this truth table, it can be observed that the higher the subscript number of the input, the higher the priority of the input. Thus, the input I3 has the highest priority. Therefore, regardless of the values of other inputs, when the input I3 is equal to 1, the output for AB is 11, i.e. 3. The input I2 has the next lower priority, and then I1, and finally I0 has the lowest priority.

We can write the Boolean expression for outputs A, B, and V from the above table as follows,

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Hence, the condition for the output V is an OR operation of all the input variables.

The interrupt cycle, also known as the interrupt process or interrupt handling, is a fundamental mechanism in computer systems that allows the processor to respond to external events or requests asynchronously.

  • Interrupts are signals sent by hardware devices or software to notify the processor of events that require immediate attention, such as the completion of an I/O operation, a hardware error, or a user input.

Interrupt cycle is very similar to the instruction cycle. At the very start, the status of flip-flop R is checked. If it is 0 there is no interrupt and CPU can continue it’s ongoing tasks. But when R=1, it denotes that the ongoing process should halt because an interrupt has occurred.

• When R=0, CPU continues it’s tasks checking the status of IEN in parallel. If it is 1, FGI and FGO are checked in a hierarchy. If any of these flip-flops are found set, R is immediately set by 1.

• When R=1, the content in PC (address of next instruction in memory) is saved at M[0] and then PC is set by 1 enabling it to point the BUN operation. The instruction at M[1] is a BUN instruction that leads the control to appropriate I/O ref. Instruction stored at some other location in the memory. Now separate Fetch, Decode and Execute phases are practiced to entertain the I/O ref. instruction.

• Once the I/O ref. instruction is executed completely, PC is loaded with 0 where it finds the saved RETURN address.

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interrupt cycle

Software routines, also known as software procedures or functions, are sets of instructions or code segments that perform a specific task or set of tasks within a software program

These routines are designed to be reusable and modular, allowing developers to efficiently manage and organize their code.

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Each interrupt service routine must have an initial and final set of operations for controlling the registers in the hardware interrupts system.

Remember that the interrupts enable IEN is cleared at the end of an interrupts cycle

The initial sequence of each interrupts service routine must have instructions to control the interrupts hardware in the following manner:

  • Clear lower-level mask register bits.
  • Clear interrupt status bit IST.
  • Save contents of processor registers.
  • Set interrupts enable bit IEN.
  • Proceed with service routine.

The final sequence of each interrupts service routine must have instructions to control the interrupts hardware in the following manner:

  • Clear interrupts enable bit IEN.
  • Restore contents of processor registers.
  • Clear the bit in the interrupts registers belonging to the source that has been serviced.
  • Set lower-level priority bits in the mask register.
  • Restore return address into PC and set IEN.

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