Asynchronous Data Transfer

Here is the explanation of Asynchronous Data Transfer:

A synchronous data transfer is a data transmitting method where data is sent in a non-continuous, non-synchronous manner.

•This shows that data is transmitted at irregular intervals, without any fixed timing or coordination between the sender and receiver.

•We synchronize the internal operations in any individual unit of the digital system using clock pulse. That means clock pulse is given to every register within the unit.

•All the data transfer among internal registers co-occurs during the occurrence of the clock pulse.

Here is a short example for Better Understanding of Asynchronous Data Transfer

 let’s assume that two units of the digital system are designed independently, like CPU and I/O interface. If the internal registers in the I/O interface share a standard clock with the CPU registers, then data transfer between the units (two or more) is said to be synchronous. But in maximum cases, the internal timing in every unit is independent of each other, so every unit uses its clock for its registers. In this case, the units are asynchronous, and data transfer between them is called Asynchronous data transfer.

Methods of Asynchronous Data Transfer:

We have four different methods of Asynchronous data transfer:

• Strobe Control Method
• Handshaking Method
• Asynchronous Serial Transfer
• Asynchronous Communication Interface
• First-In, First-Out Buffer

1.) Strobe Control Method:

Strobe control is a method used to synchronize the timing of data transmission between two devices. The strobe signal, also known as a clock signal, is used to indicate the timing of when data should be sampled or latched.

• The Strobe Control mode of asynchronous data transfer employs only one control line to time each transfer. This control line is known as a strobe, and we may achieve it either by destination or source, depending upon the one who initiates the data transfer.

‣Source initiated strobe: 

•In the below block diagram, you can see that strobe is initiated by source, and as shown in the timing diagram, the source unit first places the data on the data bus.

• After a brief delay to ensure that the data resolve to a stable value, the source activates a strobe pulse.

• The information on the data bus and strobe control signal remains in the active state for a sufficient time to allow the destination unit to receive the data.
• The destination unit uses a falling edge of strobe control to transfer the contents of a data bus to one of its internal registers.

• The source removes the data from the data bus after it disables its strobe pulse. Thus, new valid data will be available only after the strobe is enabled again.

• In this case, the strobe may be a memory-write control signal from the CPU to a memory unit. The CPU places the word on the data bus and informs the memory unit, which is the destination.

‣Destination initiated strobe:

• In the below block diagram, you see that the strobe initiated by destination, and in the timing diagram, the destination unit first activates the strobe pulse, informing the source to provide the data.

2.) Handshaking Method:

Handshaking refers to the process by which two communicating devices or systems establish and maintain synchronization during data transmission.

• The strobe method has the disadvantage that the source unit that initiates the transfer has no way of knowing whether the destination has received the data that was placed in the bus. Similarly, a destination unit that initiates the transfer has no way of knowing whether the source unit has placed data on the bus.
• So this problem is solved by the handshaking method. The handshaking method introduces a second control signal line that replays the unit that initiates the transfer.
• In this method, one control line is in the same direction as the data flow in the bus from the source to the destination. The source unit uses it to inform the destination unit whether there are valid data in the bus.
• The other control line is in the other direction from the destination to the source. This is because the destination unit uses it to inform the source whether it can accept data. And in it also, the sequence of control depends on the unit that initiates the transfer. So it means the sequence of control depends on whether the transfer is initiated by source and destination.

‣ Source initiated handshaking:

• In the below block diagram, you can see that two handshaking lines are “data valid“, which is generated by the source unit, and “data accepted“, generated by the destination unit.

• The timing diagram shows the timing relationship of the exchange of signals between the two units. The source initiates a transfer by placing data on the bus and enabling its data valid signal. The destination unit then activates the data accepted signal after it accepts the data from the bus.

• The source unit then disables its valid data signal, which invalidates the data on the bus.
After this, the destination unit disables its data accepted signal, and the system goes into its initial state. The source unit does not send the next data item until after the destination unit shows readiness to accept new data by disabling the data accepted signal.

• This sequence of events described in its sequence diagram, which shows the above sequence in which the system is present at any given time.

Destination initiated handshaking: 

• In the below block diagram, you see that the two handshaking lines are “data valid“, generated by the source unit, and “ready for data” generated by the destination unit.

• Note that the name of signal data accepted generated by the destination unit has been changed to ready for data to reflect its new meaning.

3.) Asynchronous Serial Transfer:

• The data transfer between two units can be done in either series or parallel. In parallel data transfer, every message bit has its own direction, and the whole message is sent at a similar time. This defines that an n-bit message must be sent through n separate conductor paths.
• In serial data transmission, every message bit is transmitted in sequence one by one at a time. This approach requires only one conductor or one conductor pair and common ground. The parallel transfer is quicker but requires multiple conductors. We use it for shorter distances and where speed is crucial. A serial transfer is easy and less costly as it requires only one conductor pair.
• Serial transmission can be asynchronous or synchronous. In synchronous transmission, two units transfer common clock frequency, and data bits are sent frequently at the cost decided by the clock pulses. In asynchronous serial transmission, binary data is transmitted only when required, and the line waits idly if there is no data to be sent.

Diagram of Asynchronous Serial Transfer

4.) Asynchronous Communication Interface:

• An Asynchronous communication interface functions both as a receiver and a transmitter. The interface is boot up for any specific mode of transfer using the control byte that is loaded into the control register. The transmitter register receives a data bit from the CPU by the data bus. This data bit is sent to a shift register for serial transmission.
• The receiver end receives serial information in a different shift register, and when a finalized data bit is acquired, it moves to the receiver register. The CPU may choose the receiver register to read the data bit through the data bus. The bits in the status register are utilized for output and input flags and for recording specific errors that can appear during the transmission.

Block Diagram of Asynchronous Communication Interface:

‣ Parts of Interface:

• The interface is initialized by the help of control bit loaded into the control register.
• The transmitter register accepts the data byte from CPU through data bus which is then transferred to shift register for serial transmission.
• The serial information is received into another shift register and is transferred to the receiver register when a complete data byte is accumulated.
• The bits in status register are used to check any errors during transmission and for input and output flags which can be read by the CPU.
• The chip select (CS) input is used to select interface through address bus. The register select (RS) is associated with Read (RD) and write (WR) controls.
• Two registers are read and write only. The register selected is the function of RS value and RD and WR status as shown in the table below.

‣ Working of Interface:

• The interface is initialized by the CPU by sending a byte to the control register.
• Two bits in the status register are used as flags and one bit is used to indicate whether the transmission register is empty and another bit is used to indicate whether the receiver register is full.

‣ Working of the Transmitter portion:

• The CPU reads the status register and checks the transmitter. If the transmitter is empty then CPU transfers the character to transmitter.
• The first bit in transmitter is set to 0 to generate a start bit.
• The parallel transfer of character takes place from the transmitter register to the shift register.
• The transmitter is then marked empty. The CPU can transfer another character to transmitter register after checking the flag in status register.

‣ Working of Receiver Portion:

• The receive data input is in 1-state when line is idle.
• The receiver control monitors the receive data line to detect the occurrence of a start bit. The character bits are then shifted to the shift register once the start bit has been detected.
• When the stop bit is received, the character is transferred in parallel from shift register to the receiver register.
• The interface checks for any errors during transmission and sets appropriate bits in the status register.
• The three possible errors that the interface checks are the parity error, framing error and over run error.

5.) First-In, First-Out Buffer:

A First-In, First-Out(FIFO) buffer is a memory unit that stores information in such a manner that the item first in is the item first out.

• A FIFO buffer comes with separate input and output terminals.

• The important features of this buffer is that it can input data and output data at two different rates and the output data are always in the same order in which the data entered the buffer.

Here is the logic diagram of 4*4 FIFO buffer: